A DLL (Delay Locked Loop) circuit, frequently also referred to as a phase tracking loop, is used in general to maintain a defined delay for two correlated signals. Such a DLL circuit is described in US patent specification U.S. Pat. No. 6,043,694, for example.
The ever higher demands on reliability, smaller dimensions, lower power requirement, higher processing speed and lower price for integrated circuits result in ever larger scales of integration and in the development of large scale and very large scale integrated circuits. In the course of this development, complete systems are increasingly also being produced on one chip, these being known as SOC (System On Chip) systems. Such SOC systems were intended to be used for widely differing applications so that the development complexity is kept within acceptable limits and the system can still be produced in sufficiently large numbers and hence at optimized cost. For reasons of flexibility, the chip in modern SOC architectures therefore holds only those functional units which are necessary for the different applications. The other application specific functional units can be coupled on externally using an interface as required.
Thus, modern SOC architectures use external memory chips if greater memory resources are required for the respective application than are available in the respective SOC system. These external memory chips are coupled to the SOC system via an interface and can have information read from and written to them using an interface controller which is part of the SOC system.
Such memory chips may be in the form of DDR-SDRAM (DDR=Double Data Rate; SDRAM=Synchronous Dynamic Read Access Memory) memories, for example. In contrast to conventional SDR-SDRAM (SDR=Single Data Rate) memories, the data in DDR memories are transferred not only on the rising edge but also on the falling edge of the system clock. A DDR-SDRAM memory can thus be used to transfer data at a higher frequency, that is to say that a DDR-SDRAM memory effectively operates at 200 MHz for a 100 MHz bus clock, and the transfer rate increases from, for example, 0.8 to 1.6 Gbit/s as compared with conventional SDR-SDRAM memories. The actual memory cells in DDR-SDRAM memories operate no more quickly than conventional SDR-SDRAM memories, but they are addressed in pairs and are then read in succession, which means that effectively double the data transfer rate is made possible. DDR memories thus transfer two data words in each clock cycle. This principle has been known for a long time and is used in many processors, which means that the design and operation of such memories will not be discussed in more detail below.
So that transfer of the second data word in each clock step proceeds really precisely, DDR-SDRAM memories contain an internal clock synchronization circuit, which is typically in the form of a DLL circuit. This DLL circuit produces a defined signal delay for signals to or from the externally coupled memory. So that the exact synchronism between the data signals and the clock signal is maintained during the data transfer too, a differential clock signal is used. In addition, a bidirectional clocking system is used.
Present memory technologies, such as the DDR-SDRAM memory, involve the memory chip transferring DQS signals or DQS signal changes together with the data which have been read, said DQS signals or DQS signal changes indicating that a valid data item is being applied to the bus interface and can be read therefrom. These DQS signals are transferred simultaneously with the data which are to be read. This DQS signal is used to read the data item which is to be read in clocked fashion via the bus interface.
The asynchronous character of this data item which is to be read and of the associated DQS signals means that either the clocked data item which has been read on the memory interface needs to be synchronized to the system clock associated with the SOC system or the choice of low frequencies and environment parameters which are stable over wide ranges is able to guarantee that the data item which has been read arrives at the bus interface in sync and, in the process, as little infringement of the setup time and hold time with the system clock is registered as possible. In the first case, the bandwidth for the external memory chip would be reduced by the additional synchronization stages which are required as a result. In the second case, there is a reduction in bandwidth on account of the lower maximum frequency at which the external memory chip is operated. For both cases, there is thus a lower maximum frequency and hence a lower data transfer rate. Another drawback is that a stable ambient temperature, to which the SOC system and the memory coupled thereto are exposed, are not always guaranteed.
A third option is to choose the sampling time for the data which are to be read such that it always takes place in sync with the system clock. This sampling time is obtained from the DQS signals. The sampling time obtained through the DQS signal is shifted backward in time using the DLL circuit as soon as it is too close in time to the positive clock edge of the system clock, and a “setup time” infringement could arise as a result. In this context, it is also shifted backward in time equally to such an extent that no “hold time” infringement may arise either. This can be realized by a DLL circuit which is controlled by means of the DQS signal and the system clock. These hold time and setup time periods define a “prohibited zone” in which the sampling time must not be placed, since data losses may then arise when data are being read.
Since, in this situation, the DLL circuit is controlled using signal changes in the DQS signal from the memory chip, it is necessary to ensure that this DQS signal actually changes regularly, so that the sampling time stipulated by the DQS signal can be matched to alterations in the environment parameters (for example in the temperature or in the voltage). If the DQS signals do not change over a relatively long period, then the DLL circuit and hence also the sampling time are not matched to a propagation time which has changed. Such a change in the propagation time may arise, by way of example, on account of an alteration in the voltage or in the temperature, for example in the interface controller, on the bus interface, in the memory chip etc. This propagation time change may result in a shift in the sampling time relative to the clock, however, with the consequence that the sampling time is now situated in the “prohibited time range”. If the external memory is then accessed after a relatively long time and the present setting of the DLL circuit no longer matches the propagation time for the signals from the memory chip to the interface controller, this can result in data losses.